The reason why LVDS has become the preferred signal form of high-speed i/o interface to solve the limitation of high-speed data transmission is that it has advantages in transmission speed, power consumption, anti noise, EMI and so on.

① High speed transmission capability. In the LVDS standard defined in ans/eia/eia-64, the theoretical limit rate is 1.923gbps. The constant current source mode and low swing output mode determine that IVDS has high-speed driving capability.

② Low power consumption. LVDS devices are implemented by CMOS technology, and CMOS can provide low static power consumption; When the driving current of the constant current source is 3.5ma, the power consumption of the load (100 Ω terminal matching) is only 1.225mw; The power consumption of LVDS is constant, unlike the dynamic power consumption of CMOS transceivers, which increases with respect to frequency. The constant current source mode driver design reduces the power consumption of the system and greatly reduces the influence of frequency components on power consumption. Although the power consumption of CMOS is smaller than that of LVDS when the rate is low, the power consumption of CMOS will gradually increase with the increase of frequency, and eventually more power will be consumed than that of LVDS. Generally, when the frequency is equal to 200MSPS, the power consumption of LVDS and CMOS is roughly the same.

③ Low supply voltage. With the development of integrated circuits and the requirement of higher data rate, low-voltage power supply is urgently needed. Reducing the supply voltage not only reduces the power consumption of high-density integrated circuits, but also reduces the heat dissipation pressure inside the chip, which helps to improve the integration. The driver and receiver of LVDS do not depend on the specific supply voltage characteristics, which determines that it occupies the upper peak in this aspect.

④ Strong anti noise ability. The inherent advantage of the differential signal is that the noise is coupled on a pair of differential lines in the form of common mode and subtracted in the receiver, so the noise can be eliminated. Therefore, LVDS has a strong ability to resist common mode noise.

⑤ Effectively suppress electromagnetic interference. Due to the opposite polarity of differential signals, the electromagnetic fields radiated by them can offset each other. The closer the coupling is, the less electromagnetic energy will be released to the outside, that is, EMI will be reduced.

⑥ Precise timing positioning. Because the switch change of the differential signal is located at the intersection of the two signals. Unlike ordinary single ended signals, which rely on high and low threshold voltages, they are less affected by process and temperature, which can reduce timing errors and facilitate the effective transmission of high-speed digital signals.

⑦ It adapts to the wide variation range of ground level voltage. The LVDS receiver can withstand the voltage change between the driver and the receiver of at least ± 1V. Since the typical bias voltage of the IVDS driver is +1.2v, the voltage change of the ground, the bias voltage of the driver and the noise slightly coupled to it are the sum of the common mode voltage at the input of the receiver relative to the ground of the driver. When the swing is not more than 400mV, the common mode range is +0.2v~+2.2v. In general, the input voltage range of the receiver can vary within 0v~+2.4v.

It is precisely because LVDS has the above main characteristics that HyperTransport (by AMD) [3], irfiniband (ly Intel), PCI Express (by Intel) and other third-generation i/o bus standards (3G IO) take low-voltage differential signal (IVDS) as the next-generation high-speed signal level standard.